Semiconductor integrated circuits include a plurality of microelectronic structures (e.g., transistors, diodes, and the like) formed by creating a variety of doped regions in a semiconductor wafer substrate. These regions are formed by performing a number of operations, for example, epitaxial growth, diffusion, ion implantation, etching, and the like. These devices are then interconnected by a conductive metallization layer to form a desired integrated circuit.
This invention concerns semiconductor devices that are manufactured by using a multilayer structure formed through the epitaxy of semiconductor materials of different properties and that are useful as ultrahigh frequency and ultrahigh-speed transistors. For example, applications of the present invention may be found in connection with N+contacts to laser diodes, heterojunction bipolar transistors (HBTs), light emitting diodes (LEDs), Schottky diodes, field effect transistors (FETs), metal-semiconductor field effect transistors (MESFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), and other compound semiconductor and optoelectronic devices. For purposes of illustration only, and without limitation, the present invention will be described with particular reference to its application to the manufacture of gallium arsenide (GaAs)-based HBTs having one or more layers of indium gallium arsenide (InGaAs).
In recent years, high performance HBTs have been attracting much attention for power amplifier and high-speed digital applications, including such areas as automotive radar, traffic control, and wireless applications. The general structure of and conventional fabrication processes for HBTs are well known by those skilled in the art.
HBTs are generally made up of collector, base, and emitter layers disposed to form a pair of junctions. In general, an HBT is a three-terminal device in which the upper layers (i.e., the base and emitter layers) are etched away in order to expose the underlying collector layer. Contacts are made to each of the layers to provide the three-terminal device having a collector, emitter, and a base contact.
The reliability of HBTs is directly related to the integrity of the ohmic contacts at the emitter, base, and collector layers. In particular, fabrication of contacts with excellent ohmic characteristics, namely, low contact resistance and low sheet resistance, is critical to achieving high-performance HBT integrated circuits. Primary considerations in the choice of an ohmic metallization system are low specific contact resistance, thermal stability, good morphology, good adhesion to and very shallow penetration of the contact layer into the semiconductor, and resistance to wet chemical processing. The selected metallization system for the ohmic contacts must provide the correct electrical link between the active region of the semiconductor device and the external circuit, while at the same time enabling a low-energy carrier transport through the thin interface region and ensuring a negligible series resistance in it under normal device operating conditions.
In addition, as is common in the art, the deposited ohmic contacts often are alloyed under relatively high-temperature conditions in order to drive the required metal-semiconductor interfacial reaction, or may experience high-temperature thermal cycles as may be required by subsequent processing steps in forming the integrated circuit. High-temperature alloy processes and/or thermal cycles may result in the formation of undesirable alloy “spikes” in the interfacial region of the ohmic contact and the underlying semiconductor layer. These spikes in the interfacial layers can lead to non-uniform current flow through the device and degraded microstructure. Thus, another consideration in the design of an ohmic contact system is the composition and thickness of the reactive layer of the contact system. Preferably, the reactive layer will be fashioned such that substantially all of the metal in the reactive layer reacts with the underlying semiconductor layer during the anneal process, without resulting in excessive alloy spikes or spikes that extend too far into the underlying semiconductor layer and ultimately punch through the semiconductor layer into the underlying layers of the device.
Further disadvantages of prior art fabrication techniques for ohmic contacts to GaAs-based HBTs include utilization of precious metals, such as gold and platinum, which increase raw material costs. Additionally, as the number of metallization layers deposited to form the ohmic contact structure increases, the cost of manufacturing the EBT device increases.
A method of forming contacts on GaAs-based HBTs is thus needed that minimizes contact resistance, prevents punchthrough of reactive contact metallization, reduces raw material costs by eliminating and/or minimizing the use of precious metals such as gold and platinum, and facilitates manufacturing by reducing the number of metallization layers in the contact structure, without sacrificing device performance and functionality. In particular, there exists a need in the art for a suitable ohmic contact to epitaxially grown compound semiconductor materials, such as epitaxially grown, highly N-type doped indium gallium arsenide (InGaAs) and indium arsenide (InAs), that exhibits low sheet resistance and that excludes gold or other highly conductive metal overlayers that have proven detrimental to the reliability and manufacturability of HBT devices of the prior art.